Abstract :

The most commonly used technique in networking nowadays is packet switching. It has become one of the important infrastructure elements in the communication society. Time-division multiplexing (TDM) and Synchronous Digital Hierarchy (SDH) over Ethernet is regarded as an economical and efficient scheme in the mid-distance of TDM or (SDH) interconnections. This paper focus on the design and analysis of the E1 to Ethernet protocol converter (Gateway), it based on the frame granularity scheme which takes into account of miniaturization, power, cost and time delay of companding reduction. The E1 to new Ethernet (LAN) link protocol converter designed in this paper utilizes universal programmable devices. A new approach is proposed, modeled and then simulated by using (VHDL) code and implemented in Spartan 3E kit. In high speed networks, packet processing is relatively expensive while bandwidth is cheap. The proposed approach considers the most important factor affecting the performance of high speed networks. These are packet processing time, throughput, and packet efficiency. Packet processing time is an issue in real time communications. As consequences, real time signal quality (like the voice) might be degraded severely when the process time exceed its limits. In this paper, the simulation results show that the active mode of the frame payload effectively improves the performance of the Ethernet protocol. In E1 line, 36% bandwidth is saved at half traffic load of the maximum.

Keywords: TDMoIP, TDMoE, Ethernet, E1, FPGA.