Abstract : Sigma-Delta Analog to Digital Converter with digital implementation techniques is simulated. The differential pin based and inverter based architectures are discussed. Simulation of the proposed architecture with Virtex-4 FPGA I/Os is performed and analysis carried out using HSPICE to estimate the typical achievable clock speeds. The results demonstrate 200MHz clock speeds on LVPECL differential input pin for comparator action. Subsequently MATLAB simulation is carried out to simulate the digital blocks of SD-ADC. The results show promising direction of research for realizing SD-ADCs with only passive analog components outside the FPGA/ASIC. Keywords: sigma-delta ADC, differential I/Os, all-digital-ADC, spartan-6 IBISmodel simulation, Select-IO technology, SFDR.