Abstract: Recently, the design complexity of System-on-a-chip (SoC) has increased and additional functionalities have been added to SoC. Moreover, their operation clocks are frequently transferred from single clock domain to multiple clock domains. Because of the volume of the crossing signals and the variety methods of implementing crossed clock, the verification of clock domain crossings (CDCs) has become a very important and challenging task in deep submicron designs. Therefore, specialized CDC verification solutions can accurately detect CDC issues and efficiently debug the root causes of these problems that we require to perform design analyses. This paper describes certain case studies involving CDC verification and the relationship between clock and operating frequencies. Variable combination of clock frequencies “rclk” and “wclk” was evaluated for the asynchronous first-in first-out (FIFO) memory design. When a synchronizer was inserted, the power consumption decreased with the frequency; however, the performance achieved a “dead point” when “wclk” was about 1.3 times the value of “rclk.” The results confirmed that different combinations of clock frequency affected the circuit characteristics. Keywords: System-on-a-chip; clock domain crossings; clock frequency; CDC solution; asynchronous memory