RSA Power Analysis Obfuscation: A Dynamic Algorithmic Hardware Countermeasure
وكيل مرتبط
دولة النشر
Bahrain
مكان النشر
Sakhir, Bahrain
الناشر
University of Bahrain
تاريخ النشر
2014
اللغة
الأنجليزية
الوصف
Abstract:
The modular exponentiation operation used in popular public key encryption schemes, such as RSA, has been the focus of many side channel analysis (SCA) attacks in recent years. Current SCA attack countermeasures are static, referring to the algorithmic elements as implemented in hardware. Given sufficient signal-to-noise ratio and a number of power traces, static countermeasures can be defeated, as they merely attempt to hide the power consumption of the system under attack. This paper develops a dynamic countermeasure which constantly varies the timing and power consumption of each operation, making correlation between traces more difficult. By randomizing the radix of encoding for Booth multiplication and randomizing the window size for exponentiation, we demonstrate a SCA countermeasure can be constructed which increases RSA SCA attack protection up to at least 100,000 encryption cycles, as well as a reduced execution time due to a reduction in required operations.
Keywords: Countermeasure, Side-Channels, FPGA, DPA, RSA.
The modular exponentiation operation used in popular public key encryption schemes, such as RSA, has been the focus of many side channel analysis (SCA) attacks in recent years. Current SCA attack countermeasures are static, referring to the algorithmic elements as implemented in hardware. Given sufficient signal-to-noise ratio and a number of power traces, static countermeasures can be defeated, as they merely attempt to hide the power consumption of the system under attack. This paper develops a dynamic countermeasure which constantly varies the timing and power consumption of each operation, making correlation between traces more difficult. By randomizing the radix of encoding for Booth multiplication and randomizing the window size for exponentiation, we demonstrate a SCA countermeasure can be constructed which increases RSA SCA attack protection up to at least 100,000 encryption cycles, as well as a reduced execution time due to a reduction in required operations.
Keywords: Countermeasure, Side-Channels, FPGA, DPA, RSA.
المجموعة
المعرف
https://digitalrepository.uob.edu.bh/id/e836d241-3b92-4ac9-a36f-dfe7564d2e10
https://digitalrepository.uob.edu.bh/id/e836d241-3b92-4ac9-a36f-dfe7564d2e10